The present invention relates generally to a performance monitor for integrated circuits, and more particularly to an embedded, on-chip performance monitor system that monitors the operation of a core processor associated device, such as a cache, a memory management unit (MMU) or the like.
Consumers demand the ability to be able to send and receive information at any time and from any location. There is an increasing need, therefore, for devices that are compact and mobile, such as portable wireless devices including pagers, cellular phones, and personal digital assistants (PDAs). Wireless devices usually include a microcontroller for controlling operations of the device. The device is usually battery powered, such that power management and power consumption are critical issues. Also, it is desired to optimize performance by increasing speed and processing capability as much as practicable, where processing capability is usually measured in millions of instructions per second (MIPS). The microcontroller includes an embedded core processor, also referred to as a central processing unit (CPU) or core, which executes software program instructions, commonly referred to as xe2x80x9ccode,xe2x80x9d to operate the device. It is desired to optimize code execution and code density in order to improve power utilization, increase performance, and reduce the amount of memory required for code and data storage within the device.
Certain applications and systems have been developed to debug code and improve code execution and code density. For example, circuitry complying with the On-Chip Emulation (ONCE) standard provides static debug capabilities for embedded core processor type devices such as microcontrollers. The ONCE system includes logic that directly monitors the embedded core processor and enables a developer at an external debug work station to set start and stop points during operation of the core. The developer may then monitor certain data and code after the core processor has been halted in order to perform code debug. Another system is the EEE-ISTO 5001(trademark)-1999, The Nexus 5001 Forum(trademark) (NEXUS) standard, which provides a general-purpose interface for the software development and debug of embedded core processors. In accordance with NEXUS, a developer may monitor a core bus of the embedded core processor to view data and code accesses in real-time.
Systems based on the ONCE and NEXUS standards allow a developer to monitor code flow and code behavior to generally improve code operation. Such debug capabilities, however, are not directly applicable to real-time performance monitoring and analysis of the embedded core processor and its associated devices, such as a cache. The ONCE and NEXUS systems do not allow direct and real-time monitoring of cache utilization. Analysis of cache utilization is important when trying to optimize MIPS performance of a core processor. Core processor performance and power consumption are directly affected by cache utilization. Cache utilization is affected by a number of factors, including the type of code being executed, the position of code and data in memory, and the number of times that the code and data are accessed. Cache utilization is based on the number of cache misses or the ratio of cache hits and misses. A cache miss occurs when the core processor attempts to access data or code which is not located in the cache, thus requiring an external memory access. A cache hit occurs when the data or code being accessed by the core processor is located in the cache. Cache misses cause latency and power penalties due to process or pipeline stalls when external memory must be accessed.
Existing techniques for measuring performance of devices associated with the core processor, such as a cache, are unsuitable. Modeling programs, which have been used to simulate cache performance, only provide non real-time statistics. Equipment, such as logic analyzers, may be used to externally interface to the cache to monitor cache hit signals; however, such equipment requires the microcontroller to have special pin-outs to attach the equipment off-chip. In many devices, such as cellular phones, the use of such equipment is not desired because pin count must be minimized to ensure compactness of the device. In addition, connection of on-chip logic to off-chip equipment can alter the behavior of the on-chip logic to the detriment of the evaluation.
It is desired therefore to monitor performance of core associated devices, which are indicative of processor performance, without the use of extra pin-outs or external monitoring equipment.